Vivado Red MCP

Add a breakpoint on signal edge or change.

Add XDC constraint files to the current project.

Add an IP core to the current block design (`create_bd_cell -type ip -vlnv ...`). If `config` is provided, the CONFIG.* keys are applied via set_property -dict.

Add an RTL module (Verilog/VHDL already in the project, see add_sources) to the current block design as a module-reference cell (`create_bd_cell -type module -reference`). Optional `config` sets its parameters, e.g. {'CONFIG.WIDTH': '8'}; string parameters keep their quotes, e.g. {'CONFIG.init': '"0011"'}.

Add signals to the waveform viewer.

Add HDL source files (.v/.sv/.vhd) to the current project. Optionally sets the top module and updates compile order.

Apply the Zynq-7000 processing_system7 board preset to a PS7 cell — wires FIXED_IO / DDR / clocks per the board definition. Equivalent to clicking 'Run Block Automation' on a freshly added PS7 in the GUI.

Auto-assign addresses in the BD address editor (assign_bd_address).

Use `apply_bd_automation -rule xilinx.com:bd_rule:axi4` to wire an AXI master to a slave (inserts AXI interconnect + clock/reset hookups).

Verify the Vivado process is responsive. With auto_recover=true the session is restarted if it hangs.

Close the currently open block design (without deleting).

Close the Hardware Manager.

Close the currently open project.

Close the current simulation.

Set CONFIG.* properties on an existing block-design cell (set_property -dict). Use for settings that must be applied after creation or in a separate step, e.g. importing a PS7 board preset: {'CONFIG.PCW_IMPORT_BOARD_PRESET': '<path>/red_pitaya.xml'}.

Set CONFIG.* properties on an existing IP via set_property -dict.

Connect two AXI/interface pins in the current block design.

Connect two scalar pins/ports in the current block design.

Connect to a hw_server (cs_server). Default URL is localhost:3121 — the value Vivado uses when running hw_server locally.

Create a top-level port on the current block design. Scalar or vector (`from`/`to`) via create_bd_port, or an interface port when `vlnv` is given (create_bd_intf_port, e.g. the XADC 'xilinx.com:interface:diff_analog_io_rtl:1.0'). Port names must match the constraints (XDC) of the board.

Create a new block design and make it current. Optionally sets the board_part property on the project beforehand (board_part requires the BSP to be installed in Vivado).

Create an IP from the Xilinx IP catalog. Generates a .xci file in the project's IP sources fileset. Use configure_ip + generate_ip_target afterwards, then run synth_ip if you want out-of-context synthesis.

Create a new Vivado project on disk in project mode. Defaults to the Red Pitaya STEMlab 125-14 part (xc7z010clg400-1). Call add_sources / add_constraints next, then run_synthesis.

One-shot composite: create project -> add HDL sources -> apply XDC -> synth -> impl -> write_bitstream -> generate .bit.bin. Stops on the first failing stage and returns a structured payload.

Copy a .bit.bin to a Red Pitaya over SSH/SCP and load it into the FPGA. Uses /dev/xdevcfg (works on Red Pitaya OS 1.04 + 2.00) or fpgautil (OS 2.00). No Vivado session required.

Generate the HDL wrapper for a block design and (by default) add it to sources_1 and set it as project top. Implements the canonical pattern: make_wrapper -files <bd> -top; add_files -norecurse <wrapper>; set_property top <wrapper> [current_fileset]; update_compile_order.

Generate bitstream — `launch_runs impl_1 -to_step write_bitstream` -> wait_on_run. Returns ground-truth run status and the .bit path.

Convert a .bit into a raw binary image (.bit.bin) loadable via /dev/xdevcfg on the Red Pitaya. Use after generate_bitstream.

Generate a full Vivado report to a file. Use when inline reports get truncated or you need the complete output. Returns a report_id usable with read_report_section.

Generate IP output products (synthesis + simulation by default).

Get bundled metadata for a board: part, LED pinout, absolute XDC paths, default synth flags. Use the returned absolute_path values with add_constraints. No Vivado session required.

Search for cells/instances by pattern.

Get clock information and constraints (report_clocks).

Get the design hierarchy (modules and instances), optionally filtered.

Get host hostname, free memory, and session state. Useful to check there is enough RAM before launching synthesis/implementation.

Get Vivado messages filtered by severity (error/critical/warning/all).

Search for nets by pattern (default '*').

Get top-level I/O ports of the design.

Get name, part, target language, directory of the open project.

List child scopes (hierarchy) in the simulation.

Get current value of a signal in simulation.

Get values of multiple signals matching a wildcard pattern (max 50).

Get simulation log messages filtered by severity.

List simulation objects in a scope (signals/ports/internal).

Get the current simulation time (current_time).

Return structured errors and critical warnings from a run's log (default: synth_1), plus those of every failed run (e.g. out-of-context IP runs). Use after run_synthesis fails to get a clean actionable list.

Get failing/critical timing paths. Returns structured summary by default; use detail_level=standard|full for the raw text too.

Get timing summary (WNS, TNS, WHS, THS). Returns parsed metrics by default. Use generate_full_report for raw output.

Resource utilization (LUT/FF/BRAM/DSP/IO). Parsed only by default.

Look up a topical Vivado documentation summary bundled with this server. Returns markdown content + upstream URL. Known topics: block_design, ps7_zynq, timing_constraints, synthesis_strategies, simulation_xsim, red_pitaya_125_14, redpitaya_ps_pl_flow, tcl_quoting, hw_manager, ip_integrator, pitfalls_2020_1.