Vivado Red MCP
PYPI · VIVADO-RED-MCP
Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows.
Available components
Last scanned (2 hours ago)
Scores higher than 56% of PyPI servers
Category Developer Tools
How this component scores in each security and reliability category. Every signal is checked automatically from public evidence about the published package, including repeated runs of it in an isolated sandbox, and we only credit what we can confirm. How we score → Why this is hard to score →
Supply Chain Security50
- Malware scan not yet available for this package.Unverified
- No known CVEs affecting this package version or its production dependencies.Pass
- Runs setuptools.build_meta at install time, a recognised build step with no custom scripting around it. View diagnostics → Pass
- 2 of 39 dependencies flagged as unhealthy. View diagnostics → Partial
Provenance & Transparency45
- Source repository is publicly reachable at the declared URL. View diagnostics → Pass
- Provenance check failed: no build-provenance attestation is published. See how to fix → View diagnostics → Fail
- Clear OSI-approved license (MIT).Pass
- Actively maintained (last published 6 days ago).Pass
- Disclosure check failed: no security disclosure policy was found in the source repository. See how to fix → Fail
Schema Quality & AI Usability68
- AI-judged instruction clarity (good).Pass
- Tool/resource definitions use about 6014 tokens (~64/item across 93 items; 93 tools + 0 resources), lean.Pass
- Usage-examples check failed: none of the tools include examples. See how to fix → Fail
Stability & Change Management0
- Stability not yet verified: not enough scan history yet (needs a 30-day window).Unverified
Tool Coverage93
- 100% of tools have a non-trivial description (not blank, and not just the tool's name).Pass
- 80% of tool parameters carry a description.Partial
Tool Safety75
- No prompt-injection markers were found in the server instructions, tool names or descriptions we captured.Pass
- 0 of 4 tool(s) whose name or description implies an irreversible operation declare an MCP destructiveHint annotation; "remove_breakpoints" implies "remove" and declares no destructiveHint at all, which the MCP spec reads as destructive by default. See how to fix → Fail
- An AI judge read all 93 captured unit(s) of tool text and found none that tries to manipulate the model reading it.Pass
Capabilities100
- Implements a supported MCP spec version (2025-11-25); the latest is 2026-07-28.Pass
Unverified: 1 category
A category scored 0 because we could not verify it: a data source with nothing on this package, evidence we could not reach, or a check we could not run. We only credit what we can confirm.
Every change we have recorded for this component, newest first. Security-relevant changes are always shown. ▲ marks a change for the better, ▼ a change for the worse; unmarked changes are neutral.
- 5 Nov 26 −15
- Malware scan: pass → unverified ▼ security
- 3 Nov 26 +15
- Malware scan: unverified → pass ▲ security
- 2 Nov 26 52
First indexed and scored.
Diagnostic detail from the automated scan of this channel: what the scanner observed at each step, so you can see exactly where a check passed or failed. It is informational only and never changes the trust score.
Captured 5 Nov 2026 · Analysed pypi/vivado-red-mcp@0.5.0
Provenance No attestation
The registry publishes no build provenance for this version, so there is nothing to verify.
| Result | No attestation |
|---|---|
| Ecosystem | pypi |
| Reason | No attestation published |
Background: How many MCP packages publish verified provenance →
Install scripts 1 script
| Hook | Tier | Command |
|---|---|---|
| build_backend | allowlisted | setuptools.build_meta |
Background: Why install scripts are a supply-chain risk →
Dependencies 39 packages
| Packages resolved | 39 |
|---|---|
| Stale | 2 |
| Tree resolution | Complete |
Background: SBOMs and build attestations, explained →
The tools this component advertises to a client, with an estimated token cost for each. Expand a tool to see its parameters and schema. The per-tool counts are indicative and are not scored directly; the schema's total context footprint is one signal in Schema Quality & AI Usability. A tool's description is untrusted text the model reads on every call, which is what makes this list a security surface and not just an inventory: how tool poisoning works →
launch_simulation ~35
Launch xsim in behavioral/post-synth/post-impl mode.
| Name | Type | Req | Description |
|---|---|---|---|
| mode | string | – | Simulation mode (default: behavioral) |
No output schema declared.
No examples provided.
list_bd_cells ~34
List cells in the current block design (optionally filtered).
| Name | Type | Req | Description |
|---|---|---|---|
| filter | string | – | Wildcard pattern, default '*' |
No output schema declared.
No examples provided.
list_boards ~24
List boards with bundled XDC + metadata. No Vivado session required.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
list_feature_requests ~15
List all submitted feature requests.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
list_vivado_docs ~18
List the bundled Vivado documentation topics.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
load_board_xdc ~84
Resolve a bundled board XDC and attach it to the current project. Standalone wrapper over get_board_info + add_constraints.
| Name | Type | Req | Description |
|---|---|---|---|
| board | string | yes | Board id, e.g. 'red_pitaya_125_14' |
| variant | string | – | XDC variant id (e.g. 'leds_min', 'full'). Default: 'full' |
No output schema declared.
No examples provided.
open_hw_manager ~20
Open the Hardware Manager (no JTAG connection yet).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
open_project ~34
Open an existing Vivado project (.xpr file).
| Name | Type | Req | Description |
|---|---|---|---|
| project_path | string | yes | Path to .xpr project file |
No output schema declared.
No examples provided.
program_device ~83
Program a .bit onto the first device on the JTAG chain. Sequence: open_hw_target -> set PROGRAM.FILE -> program_hw_devices. The hardware must already be connected (`open_hw_manager` + `connect_hw_server`).
| Name | Type | Req | Description |
|---|---|---|---|
| bit_file | string | yes | Absolute path to .bit |
| probes_file | string | – | Optional ILA probes .ltx file |
No output schema declared.
No examples provided.
read_report_section ~97
Read a section of a previously generated report. Provide report_id (from generate_full_report) or a direct file_path.
| Name | Type | Req | Description |
|---|---|---|---|
| file_path | string | – | – |
| num_lines | integer | – | default: 100 |
| report_id | string | – | – |
| search_pattern | string | – | Regex to locate a section; returns context around first match |
| start_line | integer | – | 1-indexed (default: 1) |
No output schema declared.
No examples provided.
refresh_hw_device ~33
Refresh the currently selected hardware device (re-reads JTAG chain state). Call after re-plugging a cable.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
regenerate_bd_layout ~23
Regenerate the block design layout (cosmetic; useful before save).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
remove_breakpoints ~20
Remove all breakpoints (remove_bps -all).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_clock_interaction ~29
Run report_clock_interaction to find cross-clock paths (timed/async/unconstrained).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_drc ~36
Run report_drc and return parsed violations list (severity/code/message). Use after place_design/route_design to catch design-rule problems.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_ip_status ~22
Get a structured snapshot of the project's IP and their upgrade status.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_methodology ~26
Run report_methodology (UltraFast methodology checks). Returns violation list grouped by severity.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_power ~40
Run report_power and return parsed totals (total/dynamic/static W) + a truncated raw block. Full output stored at /tmp/vivado_red_mcp/.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
report_qor_assessment ~23
Run report_qor_assessment (overall design quality score).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
request_feature ~65
Submit a feature request for the Vivado MCP server (persisted on disk).
| Name | Type | Req | Description |
|---|---|---|---|
| description | string | yes | What you need and why |
| priority | string | – | – |
| title | string | yes | Short title |
| use_case | string | – | Task that prompted the request |
No output schema declared.
No examples provided.
restart_simulation ~17
Restart the simulation from time 0.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
rp_build_project ~310
Build a RedPitaya PS+PL project end-to-end: run the repo's project setup TCL (creates the PS7 block design from ip/system.tcl), then synthesis, implementation and write_bitstream, then generate the .bit.bin. Returns {stage, xpr_path, bit_path, bin_path, timing}. Requires start_session first.
| Name | Type | Req | Description |
|---|---|---|---|
| defines | string | – | Extra Verilog defines passed as tclarg 1 (default: empty) |
| impl_timeout | integer | – | Implementation timeout s (default: 5400) |
| jobs | integer | – | Parallel jobs for synth/impl (default: 4) |
| model | string | – | Board model — only 'Z10' supported (default: Z10) |
| project | string | yes | Project under prj/ to build (e.g. 'v0.94', 'barebones') |
| setup_timeout | integer | – | Project-setup TCL timeout s (default: 900) |
| synth_flags | string | – | Extra synth_design flags via STEPS.SYNTH_DESIGN.ARGS.MORE_OPTIONS. Default empty. RedPitaya canonical for reproducibility: '-flatten_hierarchy none -bufg 16 -keep_equivalent_registers' (NOTE: those p… |
| synth_timeout | integer | – | Synthesis timeout s (default: 2400) |
| workspace_path | string | yes | – |
No output schema declared.
No examples provided.
rp_create_custom_project ~98
Clone an existing prj/<base> into prj/<name> inside the workspace, ready for custom PL logic. Returns the rtl/ dir and red_pitaya_top path to edit. No Vivado session required.
| Name | Type | Req | Description |
|---|---|---|---|
| base_project | string | yes | Existing project to clone (e.g. 'v0.94', 'barebones') |
| name | string | yes | New project name |
| workspace_path | string | yes | – |
No output schema declared.
No examples provided.
rp_fetch_repo ~184
Download the RedPitaya-FPGA repo from GitHub as a source zip and extract it (no git required, stdlib only). Returns repo_path to feed into rp_setup_workspace. Idempotent — pass force=true to redownload. No Vivado session required.
| Name | Type | Req | Description |
|---|---|---|---|
| dest_path | string | – | Directory to extract into. Default: current working directory. |
| force | boolean | – | If true, delete an existing extracted dir and redownload (default: false). |
| ref | string | – | Branch or tag to fetch (default: master). Extracted dir is RedPitaya-FPGA-<ref>. |
| timeout | integer | – | Download timeout in seconds (default: 600). |
| url | string | – | Override the full zip URL (e.g. a tag or a fork). If set, ref is used only for the expected dir name. |
No output schema declared.
No examples provided.
rp_list_projects ~70
List projects under prj/ of a RedPitaya workspace or repo. Flags which are Z10-capable (have ip/system.tcl or legacy ip/systemZ10.tcl). No Vivado session required.
| Name | Type | Req | Description |
|---|---|---|---|
| path | string | yes | Workspace or repo root (the dir that contains prj/) |
No output schema declared.
No examples provided.
rp_setup_workspace ~145
Copy a RedPitaya-FPGA repo into an isolated workspace so builds don't touch the pristine checkout. The copy is patched to run on the installed Vivado release (block-design version check) and without git. Idempotent — pass force=true to recopy. No Vivado session required.
| Name | Type | Req | Description |
|---|---|---|---|
| force | boolean | – | If true, delete and recopy an existing workspace (default: false) |
| repo_path | string | yes | Path to the RedPitaya-FPGA checkout (contains prj/, rtl/, brd/, *.tcl) |
| workspace_path | string | – | Destination workspace dir. Default: <repo_parent>/redpitaya_mcp_workspace |
No output schema declared.
No examples provided.
rp_workspace_info ~32
Report workspace state: projects present and which already have a built bitstream.
| Name | Type | Req | Description |
|---|---|---|---|
| workspace_path | string | yes | – |
No output schema declared.
No examples provided.
run_implementation ~67
Run implementation (opt_design -> place_design -> route_design). Returns ground-truth status from the impl_1 run object.
| Name | Type | Req | Description |
|---|---|---|---|
| jobs | integer | – | Parallel jobs (default: 4) |
| timeout | integer | – | Timeout seconds (default: 5400 = 90min). |
No output schema declared.
No examples provided.
run_simulation ~50
Run the simulation for a specified time (e.g. 100ns, 1us, all).
| Name | Type | Req | Description |
|---|---|---|---|
| time | string | yes | 100ns | 1us | 10ms | all |
No output schema declared.
No examples provided.
run_synthesis ~82
Run synthesis on the current project (reset_run -> launch_runs synth_1 -> wait_on_run). Returns ground-truth status from the run object, not just text parsing.
| Name | Type | Req | Description |
|---|---|---|---|
| jobs | integer | – | Parallel jobs (default: 4) |
| timeout | integer | – | Timeout seconds (default: 2400 = 40min). Increase for large designs. |
No output schema declared.
No examples provided.
run_tcl ~51
Execute a raw TCL command in Vivado. Use for advanced ops not covered by other tools.
| Name | Type | Req | Description |
|---|---|---|---|
| command | string | yes | TCL command to execute |
| timeout | integer | – | Optional command timeout in seconds |
No output schema declared.
No examples provided.
run_tcl_script ~71
Source a .tcl script file in the Vivado session (uses `source` under the hood). Helpful for replaying canonical Red Pitaya / Xilinx reference scripts.
| Name | Type | Req | Description |
|---|---|---|---|
| path | string | yes | Absolute path to .tcl script |
| timeout | integer | – | Optional script timeout in seconds |
No output schema declared.
No examples provided.
save_bd_design ~18
Save the currently open block design to disk.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
session_status ~24
Get statistics for the current Vivado session (commands run, timing, errors).
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
set_run_strategy ~86
Set the strategy of a synthesis or implementation run (e.g. synth_1 'Flow_PerfOptimized_high', impl_1 'Performance_NetDelay_high'). On an unknown name, Vivado's error lists the valid strategies.
| Name | Type | Req | Description |
|---|---|---|---|
| run | string | yes | Run name (e.g. synth_1, impl_1) |
| strategy | string | yes | Strategy name |
No output schema declared.
No examples provided.
set_simulation_top ~41
Set the top-level testbench module for simulation.
| Name | Type | Req | Description |
|---|---|---|---|
| fileset | string | – | default: sim_1 |
| top_module | string | yes | – |
No output schema declared.
No examples provided.
ssh_redpitaya_exec ~118
Run an arbitrary shell command on a Red Pitaya over SSH and return stdout/stderr/exit code. Useful for status checks, dmesg reads, manual loader invocations.
| Name | Type | Req | Description |
|---|---|---|---|
| command | string | yes | Shell command to execute |
| connect_timeout | integer | – | – |
| exec_timeout | integer | – | Command timeout (default: 30s) |
| host | string | yes | – |
| key_filename | string | – | – |
| password | string | – | – |
| port | integer | – | – |
| user | string | – | – |
No output schema declared.
No examples provided.
start_session ~66
Start a persistent Vivado TCL session. Must be called before project/design tools. Vivado startup is ~30s; the session is reused across tool calls.
| Name | Type | Req | Description |
|---|---|---|---|
| vivado_path | string | – | Path to vivado(.bat) executable (default: 'vivado' from PATH). |
No output schema declared.
No examples provided.
step_simulation ~26
Step simulation by delta cycles.
| Name | Type | Req | Description |
|---|---|---|---|
| count | integer | – | default: 1 |
No output schema declared.
No examples provided.
stop_session ~18
Stop the Vivado TCL session and free resources.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
synth_ip ~29
Run out-of-context (OOC) synthesis on an IP.
| Name | Type | Req | Description |
|---|---|---|---|
| module_name | string | yes | – |
No output schema declared.
No examples provided.
upgrade_ip ~39
Upgrade IP version (no-op if already at latest).
| Name | Type | Req | Description |
|---|---|---|---|
| module_name | string | – | Specific IP to upgrade; if omitted, upgrades all in project |
No output schema declared.
No examples provided.
validate_block_design ~33
Run validate_bd_design and return parsed status. Failures include unconnected pins, conflicting CONFIG values, or missing assignments.
Input schema present but exposes no named parameters.
No output schema declared.
No examples provided.
How do I install the Vivado Red MCP server?
Vivado Red MCP runs locally as a PyPI package, launched with uvx vivado-red-mcp. Ready-made configuration for Claude, Cursor, VS Code, Codex and 5 more is on this page, copied from each client's own documentation.
pypi · vivado-red-mcp
claude mcp add sinemortal-vivado-red-mcp -- uvx vivado-red-mcp
What is the Vivado Red MCP server?
Vivado Red MCP is listed in the public MCP registry as io.github.sinemortal/vivado-red-mcp. Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows. This page covers its PyPI package (vivado-red-mcp).
Is the Vivado Red MCP server safe to use?
Vivado Red MCP scores 52 out of 100 on VerifyMCP. We found no known CVEs affecting it as of 5 November 2026. That is a record of what we were able to check automatically, not an endorsement. The category breakdown on this page shows every signal behind the number, including the ones we could not confirm.
What tools does the Vivado Red MCP server expose?
Vivado Red MCP exposes 93 tools: start_session, stop_session, session_status, check_session_health, get_host_status, and 88 more. Their descriptions and schemas cost roughly 6,014 tokens of context every time the server is loaded.
Is the Vivado Red MCP server still maintained?
Vivado Red MCP is still listed as active in the MCP registry. We last reached this channel on 5 November 2026. Those dates come from our own scans of the registry and the channel itself, not from anything the publisher announced.
What licence is the Vivado Red MCP server under?
Vivado Red MCP declares the MIT licence, which is OSI-approved. That covers the source only, and says nothing about the cost of any service it calls.