# Vivado Red MCP (pypi · vivado-red-mcp)

Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows.

- Trust score: 52/100 (low)
- Registry status: active
- Liveness: live
- Owner verified: no
- Last scored: 2026-11-05

## Components

- pypi · `vivado-red-mcp`: 52/100 (this document), [markdown](https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp.md), [page](https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp)

## Channel facts

- Registry: `pypi`
- Package: `vivado-red-mcp`
- Version: `0.5.0`
- Transport: `stdio`

## Trust breakdown

How this component scores in each security and reliability category. Every signal is checked automatically from public evidence about the published package, including repeated runs of it in an isolated sandbox, and we only credit what we can confirm. Scores are 0–100 per category. Scoring method: https://verifymcp.io/docs/scoring (what has changed: https://verifymcp.io/docs/scoring/changelog)

Scored 2026-11-05.

- **Supply Chain Security**: 50/100
  - Malware scan not yet available for this package.
  - No known CVEs affecting this package version or its production dependencies.
  - Runs setuptools.build_meta at install time, a recognised build step with no custom scripting around it.
  - 2 of 39 dependencies flagged as unhealthy.
- **Provenance & Transparency**: 45/100
  - Source repository is publicly reachable at the declared URL.
  - Provenance check failed: no build-provenance attestation is published.
  - Clear OSI-approved license (MIT).
  - Actively maintained (last published 6 days ago).
  - Disclosure check failed: no security disclosure policy was found in the source repository.
- **Schema Quality & AI Usability**: 68/100
  - AI-judged instruction clarity (good).
  - Tool/resource definitions use about 6014 tokens (~64/item across 93 items; 93 tools + 0 resources), lean.
  - Usage-examples check failed: none of the tools include examples.
- **Stability & Change Management**: 0/100
  - Stability not yet verified: not enough scan history yet (needs a 30-day window).
- **Tool Coverage**: 93/100
  - 100% of tools have a non-trivial description (not blank, and not just the tool's name).
  - 80% of tool parameters carry a description.
- **Tool Safety**: 75/100
  - No prompt-injection markers were found in the server instructions, tool names or descriptions we captured.
  - 0 of 4 tool(s) whose name or description implies an irreversible operation declare an MCP destructiveHint annotation; "remove_breakpoints" implies "remove" and declares no destructiveHint at all, which the MCP spec reads as destructive by default.
  - An AI judge read all 93 captured unit(s) of tool text and found none that tries to manipulate the model reading it.
- **Capabilities**: 100/100
  - Implements a supported MCP spec version (2025-11-25); the latest is 2026-07-28.

**Unverified: 1 category.** A category scored 0 because we could not verify it: a data source with nothing on this package, evidence we could not reach, or a check we could not run. We only credit what we can confirm.

## Install

### How do I install the Vivado Red MCP server?

Vivado Red MCP runs locally as a PyPI package, launched with uvx vivado-red-mcp. Ready-made configuration for Claude, Cursor, VS Code, Codex and 5 more is on this page, copied from each client's own documentation.

### Claude

```bash
claude mcp add sinemortal-vivado-red-mcp -- uvx vivado-red-mcp
```

### Cursor

```json
{
  "mcpServers": {
    "sinemortal-vivado-red-mcp": {
      "command": "uvx",
      "args": [
        "vivado-red-mcp"
      ]
    }
  }
}
```

### VS Code

```json
{
  "servers": {
    "sinemortal-vivado-red-mcp": {
      "command": "uvx",
      "args": [
        "vivado-red-mcp"
      ]
    }
  }
}
```

### Codex

```bash
codex mcp add sinemortal-vivado-red-mcp -- uvx vivado-red-mcp
```

### opencode

```json
{
  "$schema": "https://opencode.ai/config.json",
  "mcp": {
    "sinemortal-vivado-red-mcp": {
      "type": "local",
      "command": [
        "uvx",
        "vivado-red-mcp"
      ],
      "enabled": true
    }
  }
}
```

### OpenClaw

```bash
openclaw mcp add sinemortal-vivado-red-mcp --command uvx --arg vivado-red-mcp
```

### Hermes

```yaml
mcp_servers:
  sinemortal-vivado-red-mcp:
    command: "uvx"
    args: ["vivado-red-mcp"]
```

### Netclaw

```json
{
  "McpServers": {
    "sinemortal-vivado-red-mcp": {
      "Transport": "stdio",
      "Command": "uvx",
      "Arguments": [
        "vivado-red-mcp"
      ]
    }
  }
}
```

### Vellum

```bash
assistant mcp add sinemortal-vivado-red-mcp -t stdio -c uvx -a vivado-red-mcp
```

### Other

```json
{
  "mcpServers": {
    "sinemortal-vivado-red-mcp": {
      "command": "uvx",
      "args": [
        "vivado-red-mcp"
      ]
    }
  }
}
```

## Changelog

Every change recorded for this component, newest first. Days that predate change tracking, or that we cannot explain, say so: "we were watching and nothing happened" and "we were not watching" are different claims.

### 2026-11-05 (score 52, −15)

- [security regression] Malware scan: pass → unverified

### 2026-11-03 (score 67, +15)

- [security improvement] Malware scan: unverified → pass

### 2026-11-02 (score 52)

First indexed and scored.

## MCP tools (93)

### `start_session` (~66 tokens)

Start a persistent Vivado TCL session. Must be called before project/design tools. Vivado startup is ~30s; the session is reused across tool calls.

Input parameters:

- `vivado_path` (string): Path to vivado(.bat) executable (default: 'vivado' from PATH).

### `stop_session` (~18 tokens)

Stop the Vivado TCL session and free resources.

### `session_status` (~24 tokens)

Get statistics for the current Vivado session (commands run, timing, errors).

### `check_session_health` (~47 tokens)

Verify the Vivado process is responsive. With auto_recover=true the session is restarted if it hangs.

Input parameters:

- `auto_recover` (boolean): Restart session if unhealthy (default: true)

### `get_host_status` (~33 tokens)

Get host hostname, free memory, and session state. Useful to check there is enough RAM before launching synthesis/implementation.

### `open_project` (~34 tokens)

Open an existing Vivado project (.xpr file).

Input parameters:

- `project_path` (string, required): Path to .xpr project file

### `close_project` (~14 tokens)

Close the currently open project.

### `get_project_info` (~23 tokens)

Get name, part, target language, directory of the open project.

### `create_project` (~140 tokens)

Create a new Vivado project on disk in project mode. Defaults to the Red Pitaya STEMlab 125-14 part (xc7z010clg400-1). Call add_sources / add_constraints next, then run_synthesis.

Input parameters:

- `directory` (string, required): Parent directory; project created at <directory>/<name>
- `force` (boolean): Overwrite existing project (default: true)
- `name` (string, required): Project name
- `part` (string): Xilinx part number (default: xc7z010clg400-1)
- `target_language` (string): Verilog or VHDL (default: Verilog)

### `add_sources` (~86 tokens)

Add HDL source files (.v/.sv/.vhd) to the current project. Optionally sets the top module and updates compile order.

Input parameters:

- `files` (array, required): Absolute paths to HDL source files
- `fileset` (string): Target fileset (default: sources_1)
- `set_top` (string): If given, set this module as project top after adding files

### `add_constraints` (~49 tokens)

Add XDC constraint files to the current project.

Input parameters:

- `files` (array, required): Absolute paths to .xdc files
- `fileset` (string): Target fileset (default: constrs_1)

### `list_boards` (~24 tokens)

List boards with bundled XDC + metadata. No Vivado session required.

### `get_board_info` (~69 tokens)

Get bundled metadata for a board: part, LED pinout, absolute XDC paths, default synth flags. Use the returned absolute_path values with add_constraints. No Vivado session required.

Input parameters:

- `board` (string, required): Board identifier, e.g. 'red_pitaya_125_14'

### `run_synthesis` (~82 tokens)

Run synthesis on the current project (reset_run -> launch_runs synth_1 -> wait_on_run). Returns ground-truth status from the run object, not just text parsing.

Input parameters:

- `jobs` (integer): Parallel jobs (default: 4)
- `timeout` (integer): Timeout seconds (default: 2400 = 40min). Increase for large designs.

### `run_implementation` (~67 tokens)

Run implementation (opt_design -> place_design -> route_design). Returns ground-truth status from the impl_1 run object.

Input parameters:

- `jobs` (integer): Parallel jobs (default: 4)
- `timeout` (integer): Timeout seconds (default: 5400 = 90min).

### `generate_bitstream` (~59 tokens)

Generate bitstream — `launch_runs impl_1 -to_step write_bitstream` -> wait_on_run. Returns ground-truth run status and the .bit path.

Input parameters:

- `timeout` (integer): Timeout in seconds (default: 3600)

### `set_run_strategy` (~86 tokens)

Set the strategy of a synthesis or implementation run (e.g. synth_1 'Flow_PerfOptimized_high', impl_1 'Performance_NetDelay_high'). On an unknown name, Vivado's error lists the valid strategies.

Input parameters:

- `run` (string, required): Run name (e.g. synth_1, impl_1)
- `strategy` (string, required): Strategy name

### `get_timing_summary` (~78 tokens)

Get timing summary (WNS, TNS, WHS, THS). Returns parsed metrics by default. Use generate_full_report for raw output.

Input parameters:

- `detail_level` (string): summary | standard (+ truncated raw) | full (+ complete raw)
- `report_type` (string): summary (default), setup, hold, or all

### `get_timing_paths` (~151 tokens)

Get failing/critical timing paths. Returns structured summary by default; use detail_level=standard|full for the raw text too.

Input parameters:

- `clock` (string): Filter by clock domain
- `detail_level` (string): summary (default) | standard | full
- `from_pin` (string): Filter -from pattern
- `num_paths` (integer): Number of paths (default: 10)
- `path_type` (string): setup (default) or hold
- `slack_threshold` (number): Only show paths with slack < this (default: 0 = failing paths)
- `through` (string): Filter -through pattern
- `to_pin` (string): Filter -to pattern

### `get_utilization` (~81 tokens)

Resource utilization (LUT/FF/BRAM/DSP/IO). Parsed only by default.

Input parameters:

- `detail_level` (string)
- `hierarchical` (boolean): Hierarchical breakdown (default: false)
- `module_filter` (string): Wildcard for hierarchical filter
- `threshold_percent` (number): Mark resources below this util%% as below_threshold

### `get_clocks` (~19 tokens)

Get clock information and constraints (report_clocks).

### `get_messages` (~40 tokens)

Get Vivado messages filtered by severity (error/critical/warning/all).

Input parameters:

- `severity` (string): all (default) | error | critical | warning

### `get_design_hierarchy` (~62 tokens)

Get the design hierarchy (modules and instances), optionally filtered.

Input parameters:

- `instance_pattern` (string): Wildcard pattern (e.g., '*cpu*', 'core/alu/*')
- `max_depth` (integer): Max hierarchy depth (default: 3)

### `get_ports` (~18 tokens)

Get top-level I/O ports of the design.

### `get_nets` (~46 tokens)

Search for nets by pattern (default '*').

Input parameters:

- `limit` (integer): Max results (default: 100)
- `pattern` (string): Wildcard pattern (default: '*')

### `get_cells` (~44 tokens)

Search for cells/instances by pattern.

Input parameters:

- `limit` (integer): Max results (default: 100)
- `pattern` (string): Wildcard pattern (default: '*')

### `launch_simulation` (~35 tokens)

Launch xsim in behavioral/post-synth/post-impl mode.

Input parameters:

- `mode` (string): Simulation mode (default: behavioral)

### `run_simulation` (~50 tokens)

Run the simulation for a specified time (e.g. 100ns, 1us, all).

Input parameters:

- `time` (string, required): 100ns | 1us | 10ms | all

### `restart_simulation` (~17 tokens)

Restart the simulation from time 0.

### `close_simulation` (~14 tokens)

Close the current simulation.

### `get_simulation_time` (~19 tokens)

Get the current simulation time (current_time).

### `get_signal_value` (~42 tokens)

Get current value of a signal in simulation.

Input parameters:

- `radix` (string): Display radix (default: hex)
- `signal` (string, required): Hierarchical signal path

### `get_signal_values` (~47 tokens)

Get values of multiple signals matching a wildcard pattern (max 50).

Input parameters:

- `pattern` (string, required): Signal pattern, e.g. /tb/dut/*
- `radix` (string)

### `add_signals_to_wave` (~25 tokens)

Add signals to the waveform viewer.

Input parameters:

- `signals` (array, required)

### `set_simulation_top` (~41 tokens)

Set the top-level testbench module for simulation.

Input parameters:

- `fileset` (string): default: sim_1
- `top_module` (string, required)

### `get_simulation_objects` (~38 tokens)

List simulation objects in a scope (signals/ports/internal).

Input parameters:

- `filter` (string)
- `scope` (string): default: /

### `get_scopes` (~29 tokens)

List child scopes (hierarchy) in the simulation.

Input parameters:

- `parent` (string): default: /

### `step_simulation` (~26 tokens)

Step simulation by delta cycles.

Input parameters:

- `count` (integer): default: 1

### `add_breakpoint` (~32 tokens)

Add a breakpoint on signal edge or change.

Input parameters:

- `condition` (string)
- `signal` (string, required)

### `remove_breakpoints` (~20 tokens)

Remove all breakpoints (remove_bps -all).

### `get_simulation_messages` (~25 tokens)

Get simulation log messages filtered by severity.

Input parameters:

- `severity` (string)

### `run_tcl` (~51 tokens)

Execute a raw TCL command in Vivado. Use for advanced ops not covered by other tools.

Input parameters:

- `command` (string, required): TCL command to execute
- `timeout` (integer): Optional command timeout in seconds

### `run_tcl_script` (~71 tokens)

Source a .tcl script file in the Vivado session (uses `source` under the hood). Helpful for replaying canonical Red Pitaya / Xilinx reference scripts.

Input parameters:

- `path` (string, required): Absolute path to .tcl script
- `timeout` (integer): Optional script timeout in seconds

### `create_block_design` (~94 tokens)

Create a new block design and make it current. Optionally sets the board_part property on the project beforehand (board_part requires the BSP to be installed in Vivado).

Input parameters:

- `board_part` (string): Optional vendor:board:part string (e.g. 'digilentinc.com:arty-a7-35:part0:1.0')
- `name` (string, required): Block design name (no .bd)

### `save_bd_design` (~18 tokens)

Save the currently open block design to disk.

### `close_bd_design` (~19 tokens)

Close the currently open block design (without deleting).

### `list_bd_cells` (~34 tokens)

List cells in the current block design (optionally filtered).

Input parameters:

- `filter` (string): Wildcard pattern, default '*'

### `add_ip_to_bd` (~133 tokens)

Add an IP core to the current block design (`create_bd_cell -type ip -vlnv ...`). If `config` is provided, the CONFIG.* keys are applied via set_property -dict.

Input parameters:

- `cell_name` (string, required): Instance name (e.g. 'processing_system7_0')
- `config` (object): Dict of CONFIG.* properties (e.g. {'CONFIG.PCW_USE_M_AXI_GP0': '1'})
- `vlnv` (string, required): Vendor:Library:Name:Version (e.g. 'xilinx.com:ip:processing_system7:5.5')

### `create_bd_port` (~221 tokens)

Create a top-level port on the current block design. Scalar or vector (`from`/`to`) via create_bd_port, or an interface port when `vlnv` is given (create_bd_intf_port, e.g. the XADC 'xilinx.com:interface:diff_analog_io_rtl:1.0'). Port names must match the constraints (XDC) of the board.

Input parameters:

- `direction` (string): Direction for a plain port (default: I)
- `from` (integer): MSB index for a vector port (e.g. 7)
- `mode` (string): Interface mode (default: Slave): Master, Slave, ...
- `name` (string, required): Port name (e.g. 'led_o')
- `to` (integer): LSB index for a vector port (default: 0)
- `type` (string): Optional port type: clk, rst, ce, intr, data, undef
- `vlnv` (string): Interface VLNV: creates an interface port instead

### `add_module_to_bd` (~126 tokens)

Add an RTL module (Verilog/VHDL already in the project, see add_sources) to the current block design as a module-reference cell (`create_bd_cell -type module -reference`). Optional `config` sets its parameters, e.g. {'CONFIG.WIDTH': '8'}; string parameters keep their quotes, e.g. {'CONFIG.init': '"0011"'}.

Input parameters:

- `cell_name` (string, required): Instance name in the BD
- `config` (object): Dict of CONFIG.* parameters
- `module` (string, required): Top module name of the RTL

### `configure_bd_cell` (~89 tokens)

Set CONFIG.* properties on an existing block-design cell (set_property -dict). Use for settings that must be applied after creation or in a separate step, e.g. importing a PS7 board preset: {'CONFIG.PCW_IMPORT_BOARD_PRESET': '<path>/red_pitaya.xml'}.

Input parameters:

- `cell_name` (string, required)
- `config` (object, required): Dict of CONFIG.* properties

### `connect_bd_net` (~62 tokens)

Connect two scalar pins/ports in the current block design.

Input parameters:

- `pin_from` (string, required): e.g. 'processing_system7_0/FCLK_CLK0'
- `pin_to` (string, required): e.g. 'axi_gpio_0/s_axi_aclk'

### `connect_bd_intf_net` (~64 tokens)

Connect two AXI/interface pins in the current block design.

Input parameters:

- `intf_from` (string, required): e.g. 'processing_system7_0/M_AXI_GP0'
- `intf_to` (string, required): e.g. 'axi_gpio_0/S_AXI'

### `auto_connect_axi` (~98 tokens)

Use `apply_bd_automation -rule xilinx.com:bd_rule:axi4` to wire an AXI master to a slave (inserts AXI interconnect + clock/reset hookups).

Input parameters:

- `master` (string, required): AXI master intf pin
- `options` (object): Optional extra -config key/value pairs (e.g. {'Clk_master': 'Auto'})
- `slave` (string, required): AXI slave intf pin

### `apply_ps7_preset` (~102 tokens)

Apply the Zynq-7000 processing_system7 board preset to a PS7 cell — wires FIXED_IO / DDR / clocks per the board definition. Equivalent to clicking 'Run Block Automation' on a freshly added PS7 in the GUI.

Input parameters:

- `apply_board_preset` (boolean): Whether to apply the current board preset (default: true)
- `cell` (string): PS7 cell name (default: 'processing_system7_0')

### `validate_block_design` (~33 tokens)

Run validate_bd_design and return parsed status. Failures include unconnected pins, conflicting CONFIG values, or missing assignments.

### `regenerate_bd_layout` (~23 tokens)

Regenerate the block design layout (cosmetic; useful before save).

### `assign_bd_address` (~23 tokens)

Auto-assign addresses in the BD address editor (assign_bd_address).

### `generate_bd_wrapper` (~108 tokens)

Generate the HDL wrapper for a block design and (by default) add it to sources_1 and set it as project top. Implements the canonical pattern: make_wrapper -files <bd> -top; add_files -norecurse <wrapper>; set_property top <wrapper> [current_fileset]; update_compile_order.

Input parameters:

- `bd_name` (string, required): Block design name (no .bd)
- `set_top` (boolean): Also set the wrapper as project top (default: true)

### `create_ip` (~126 tokens)

Create an IP from the Xilinx IP catalog. Generates a .xci file in the project's IP sources fileset. Use configure_ip + generate_ip_target afterwards, then run synth_ip if you want out-of-context synthesis.

Input parameters:

- `ip_name` (string, required): Catalog name (e.g. 'clk_wiz')
- `library` (string): default: ip
- `module_name` (string, required): Instance/module name on disk (e.g. 'clk_wiz_0')
- `vendor` (string): default: xilinx.com
- `version` (string): Optional explicit version

### `configure_ip` (~57 tokens)

Set CONFIG.* properties on an existing IP via set_property -dict.

Input parameters:

- `config` (object, required): Dict of CONFIG.* keys to values (e.g. {'CONFIG.PRIM_IN_FREQ': '125'})
- `module_name` (string, required)

### `generate_ip_target` (~44 tokens)

Generate IP output products (synthesis + simulation by default).

Input parameters:

- `module_name` (string, required)
- `targets` (array): default: ['synthesis', 'simulation']

### `synth_ip` (~29 tokens)

Run out-of-context (OOC) synthesis on an IP.

Input parameters:

- `module_name` (string, required)

### `upgrade_ip` (~39 tokens)

Upgrade IP version (no-op if already at latest).

Input parameters:

- `module_name` (string): Specific IP to upgrade; if omitted, upgrades all in project

### `report_ip_status` (~22 tokens)

Get a structured snapshot of the project's IP and their upgrade status.

### `open_hw_manager` (~20 tokens)

Open the Hardware Manager (no JTAG connection yet).

### `close_hw_manager` (~14 tokens)

Close the Hardware Manager.

### `connect_hw_server` (~54 tokens)

Connect to a hw_server (cs_server). Default URL is localhost:3121 — the value Vivado uses when running hw_server locally.

Input parameters:

- `url` (string): host:port (default: localhost:3121)

### `refresh_hw_device` (~33 tokens)

Refresh the currently selected hardware device (re-reads JTAG chain state). Call after re-plugging a cable.

### `program_device` (~83 tokens)

Program a .bit onto the first device on the JTAG chain. Sequence: open_hw_target -> set PROGRAM.FILE -> program_hw_devices. The hardware must already be connected (`open_hw_manager` + `connect_hw_server`).

Input parameters:

- `bit_file` (string, required): Absolute path to .bit
- `probes_file` (string): Optional ILA probes .ltx file

### `report_power` (~40 tokens)

Run report_power and return parsed totals (total/dynamic/static W) + a truncated raw block. Full output stored at /tmp/vivado_red_mcp/.

### `report_drc` (~36 tokens)

Run report_drc and return parsed violations list (severity/code/message). Use after place_design/route_design to catch design-rule problems.

### `report_methodology` (~26 tokens)

Run report_methodology (UltraFast methodology checks). Returns violation list grouped by severity.

### `report_qor_assessment` (~23 tokens)

Run report_qor_assessment (overall design quality score).

### `report_clock_interaction` (~29 tokens)

Run report_clock_interaction to find cross-clock paths (timed/async/unconstrained).

### `load_board_xdc` (~84 tokens)

Resolve a bundled board XDC and attach it to the current project. Standalone wrapper over get_board_info + add_constraints.

Input parameters:

- `board` (string, required): Board id, e.g. 'red_pitaya_125_14'
- `variant` (string): XDC variant id (e.g. 'leds_min', 'full'). Default: 'full'

### `generate_cfgmem` (~76 tokens)

Convert a .bit into a raw binary image (.bit.bin) loadable via /dev/xdevcfg on the Red Pitaya. Use after generate_bitstream.

Input parameters:

- `bit_file` (string, required): Absolute path to input .bit
- `output` (string): Output .bit.bin path (default: <bit_file>.bin)

### `get_synthesis_errors_parsed` (~83 tokens)

Return structured errors and critical warnings from a run's log (default: synth_1), plus those of every failed run (e.g. out-of-context IP runs). Use after run_synthesis fails to get a clean actionable list.

Input parameters:

- `max_items` (integer): default: 50
- `run` (string): default: synth_1

### `create_redpitaya_project_rtl` (~151 tokens)

One-shot composite: create project -> add HDL sources -> apply XDC -> synth -> impl -> write_bitstream -> generate .bit.bin. Stops on the first failing stage and returns a structured payload.

Input parameters:

- `board` (string): default: red_pitaya_125_14
- `directory` (string, required)
- `extra_xdc_files` (array)
- `impl_timeout` (integer)
- `jobs` (integer)
- `name` (string, required)
- `synth_flags` (string)
- `synth_timeout` (integer)
- `top_module` (string, required)
- `verilog_files` (array, required)
- `xdc_variant` (string)

### `rp_fetch_repo` (~184 tokens)

Download the RedPitaya-FPGA repo from GitHub as a source zip and extract it (no git required, stdlib only). Returns repo_path to feed into rp_setup_workspace. Idempotent — pass force=true to redownload. No Vivado session required.

Input parameters:

- `dest_path` (string): Directory to extract into. Default: current working directory.
- `force` (boolean): If true, delete an existing extracted dir and redownload (default: false).
- `ref` (string): Branch or tag to fetch (default: master). Extracted dir is RedPitaya-FPGA-<ref>.
- `timeout` (integer): Download timeout in seconds (default: 600).
- `url` (string): Override the full zip URL (e.g. a tag or a fork). If set, ref is used only for the expected dir name.

### `rp_setup_workspace` (~145 tokens)

Copy a RedPitaya-FPGA repo into an isolated workspace so builds don't touch the pristine checkout. The copy is patched to run on the installed Vivado release (block-design version check) and without git. Idempotent — pass force=true to recopy. No Vivado session required.

Input parameters:

- `force` (boolean): If true, delete and recopy an existing workspace (default: false)
- `repo_path` (string, required): Path to the RedPitaya-FPGA checkout (contains prj/, rtl/, brd/, *.tcl)
- `workspace_path` (string): Destination workspace dir. Default: <repo_parent>/redpitaya_mcp_workspace

### `rp_list_projects` (~70 tokens)

List projects under prj/ of a RedPitaya workspace or repo. Flags which are Z10-capable (have ip/system.tcl or legacy ip/systemZ10.tcl). No Vivado session required.

Input parameters:

- `path` (string, required): Workspace or repo root (the dir that contains prj/)

### `rp_workspace_info` (~32 tokens)

Report workspace state: projects present and which already have a built bitstream.

Input parameters:

- `workspace_path` (string, required)

### `rp_create_custom_project` (~98 tokens)

Clone an existing prj/<base> into prj/<name> inside the workspace, ready for custom PL logic. Returns the rtl/ dir and red_pitaya_top path to edit. No Vivado session required.

Input parameters:

- `base_project` (string, required): Existing project to clone (e.g. 'v0.94', 'barebones')
- `name` (string, required): New project name
- `workspace_path` (string, required)

### `rp_build_project` (~310 tokens)

Build a RedPitaya PS+PL project end-to-end: run the repo's project setup TCL (creates the PS7 block design from ip/system.tcl), then synthesis, implementation and write_bitstream, then generate the .bit.bin. Returns {stage, xpr_path, bit_path, bin_path, timing}. Requires start_session first.

Input parameters:

- `defines` (string): Extra Verilog defines passed as tclarg 1 (default: empty)
- `impl_timeout` (integer): Implementation timeout s (default: 5400)
- `jobs` (integer): Parallel jobs for synth/impl (default: 4)
- `model` (string): Board model — only 'Z10' supported (default: Z10)
- `project` (string, required): Project under prj/ to build (e.g. 'v0.94', 'barebones')
- `setup_timeout` (integer): Project-setup TCL timeout s (default: 900)
- `synth_flags` (string): Extra synth_design flags via STEPS.SYNTH_DESIGN.ARGS.MORE_OPTIONS. Default empty. RedPitaya canonical for reproducibility: '-flatten_hierarchy none -bufg 16 -keep_equivalent_registers' (NOTE: those p…
- `synth_timeout` (integer): Synthesis timeout s (default: 2400)
- `workspace_path` (string, required)

### `deploy_to_redpitaya` (~293 tokens)

Copy a .bit.bin to a Red Pitaya over SSH/SCP and load it into the FPGA. Uses /dev/xdevcfg (works on Red Pitaya OS 1.04 + 2.00) or fpgautil (OS 2.00). No Vivado session required.

Input parameters:

- `bit_bin_path` (string, required): Absolute path to the local .bit.bin produced by generate_cfgmem
- `connect_timeout` (integer): SSH connect timeout in seconds (default: 10)
- `host` (string, required): Red Pitaya IP or hostname (e.g. '192.168.1.100' or 'rp-f0abcd.local')
- `keep_remote` (boolean): Leave the .bit.bin on the board after loading (default: false → rm)
- `key_filename` (string): Path to an SSH private key. If set, overrides password auth.
- `method` (string): Loader: 'xdevcfg' (default, both OS) or 'fpgautil' (OS 2.00)
- `password` (string): SSH password (default: 'root' — Red Pitaya factory default)
- `port` (integer): SSH port (default: 22)
- `remote_path` (string): Remote .bit.bin path (default: /tmp/<basename>)
- `user` (string): SSH user (default: 'root')

### `ssh_redpitaya_exec` (~118 tokens)

Run an arbitrary shell command on a Red Pitaya over SSH and return stdout/stderr/exit code. Useful for status checks, dmesg reads, manual loader invocations.

Input parameters:

- `command` (string, required): Shell command to execute
- `connect_timeout` (integer)
- `exec_timeout` (integer): Command timeout (default: 30s)
- `host` (string, required)
- `key_filename` (string)
- `password` (string)
- `port` (integer)
- `user` (string)

### `get_vivado_doc` (~130 tokens)

Look up a topical Vivado documentation summary bundled with this server. Returns markdown content + upstream URL. Known topics: block_design, ps7_zynq, timing_constraints, synthesis_strategies, simulation_xsim, red_pitaya_125_14, redpitaya_ps_pl_flow, tcl_quoting, hw_manager, ip_integrator, pitfalls_2020_1.

Input parameters:

- `topic` (string, required): Topic name; see KNOWN_TOPICS in the tool description
- `version` (string): Target Vivado version (cosmetic, default '2020.1')

### `list_vivado_docs` (~18 tokens)

List the bundled Vivado documentation topics.

### `request_feature` (~65 tokens)

Submit a feature request for the Vivado MCP server (persisted on disk).

Input parameters:

- `description` (string, required): What you need and why
- `priority` (string)
- `title` (string, required): Short title
- `use_case` (string): Task that prompted the request

### `list_feature_requests` (~15 tokens)

List all submitted feature requests.

### `generate_full_report` (~81 tokens)

Generate a full Vivado report to a file. Use when inline reports get truncated or you need the complete output. Returns a report_id usable with read_report_section.

Input parameters:

- `options` (object): Report-specific options (e.g. {hierarchical: true})
- `output_file` (string): Optional custom output path
- `report_type` (string, required)

### `read_report_section` (~97 tokens)

Read a section of a previously generated report. Provide report_id (from generate_full_report) or a direct file_path.

Input parameters:

- `file_path` (string)
- `num_lines` (integer): default: 100
- `report_id` (string)
- `search_pattern` (string): Regex to locate a section; returns context around first match
- `start_line` (integer): 1-indexed (default: 1)

## Diagnostics

Captured diagnostic sections: Provenance, Install scripts, Dependencies. The full working is on the page: https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp#diagnostics

## Score history

- 2026-11-05: 52
- 2026-11-04: 67
- 2026-11-03: 67
- 2026-11-02: 52

## Common questions

### What is the Vivado Red MCP server?

Vivado Red MCP is listed in the public MCP registry as io.github.sinemortal/vivado-red-mcp. Drive AMD Vivado from AI assistants, with Red Pitaya STEMlab 125-14 build and deploy flows. This page covers its PyPI package (vivado-red-mcp).

### Is the Vivado Red MCP server safe to use?

Vivado Red MCP scores 52 out of 100 on VerifyMCP. We found no known CVEs affecting it as of 5 November 2026. That is a record of what we were able to check automatically, not an endorsement. The category breakdown on this page shows every signal behind the number, including the ones we could not confirm.

### What tools does the Vivado Red MCP server expose?

Vivado Red MCP exposes 93 tools: start_session, stop_session, session_status, check_session_health, get_host_status, and 88 more. Their descriptions and schemas cost roughly 6,014 tokens of context every time the server is loaded.

### Is the Vivado Red MCP server still maintained?

Vivado Red MCP is still listed as active in the MCP registry. We last reached this channel on 5 November 2026. Those dates come from our own scans of the registry and the channel itself, not from anything the publisher announced.

### What licence is the Vivado Red MCP server under?

Vivado Red MCP declares the MIT licence, which is OSI-approved. That covers the source only, and says nothing about the cost of any service it calls.

## Links

- PyPI project: https://pypi.org/project/vivado-red-mcp/
- Socket report: https://socket.dev/pypi/package/vivado-red-mcp
- Repository: https://github.com/sinemortal/vivado-red-mcp
- Changelog RSS feed: https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp.xml
- Changelog JSON feed: https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp.json
- HTML version of this page: https://verifymcp.io/servers/sinemortal-vivado-red-mcp/vivado-red-mcp