Multisim MCP

Use the Bode Plotter adapter on an AC-sweep experiment.

Use the Logic Analyzer adapter to digitize traces and list edges.

Record explicit human approval for a complete component resolution. This is still a review artifact. It does not generate SPICE, create a CircuitDesign, write a file, render a schematic, or start a simulation; those actions require a later compiler and separate approval gates.

Record explicit human approval for one immutable netlist preview. The approval binds the compiled CircuitDesign and SPICE digest. It does not write a schematic, create a project file, add stimuli, or start a simulation; those remain separate downstream gates.

Record explicit approval for one safe simulation plan. The artifact binds the approved executable-netlist preview to the exact analysis commands, measurement requirements, and theoretical values in an ``ExperimentSpec``. It does not create a schematic, write files, or start a simulation; ``run_verified_circuit_experiment`` must validate it again.

Audit SPICE dialect, model hashes/licenses, and static backend risks.

Autonomously diagnose, propose, simulate, and select a repair candidate. The configured model may propose bounded parameter or topology patches, but every candidate is revalidated and simulated locally. The final all-pass candidate is returned as one reversible patch against the original design; applying it remains a separate explicit approval operation.

Convert supported native DFF carriers into an explicit ngspice reference. The returned netlist is not run automatically and never replaces the source design. It maps native ``D, ~PR, ~CLR, CLK, Q, ~Q, GND, VCC`` pins to the portable ``@DFF`` adapter, inserts explicit control inverters for active-low ``~PR/~CLR``, and records the behavioral-only claim. Pass the returned ``netlist`` explicitly to ``run_spice_netlist`` with ``backend='ngspice'`` when a reference run is desired.

Return the bilingual five-waveform course-design contract. With no arguments this returns the safe behavioral reference model. A caller may provide a native Multisim-compatible netlist and analysis commands to keep the same explicit requirement gates while changing the implementation. This tool only builds/validates the contract; use ``run_verified_circuit_experiment`` for measured evidence.

Cancel a queued job or safely stop its isolated worker process.

Return name, file, simulation state, and last error for the open circuit.

Clear injected data from a simulation input.

Rank 2-16 complete designs using one evidence-backed experiment contract. Each item must contain exactly ``variant_id`` and ``design``. All requirements are hard constraints, only finite measured passes are ranked, and no source design is modified or automatically adopted.

Numerically compare common signals from two registered EDA experiments.

Compile an approved logical draft into a bounded pin-level preview. Only options in the compiler support matrix are accepted. External model bytes, when present, are re-hashed beneath ``MULTISIM_MCP_MODEL_ROOT``. The result stays in memory and does not write files, create a schematic, start Multisim, or run a simulation.

List portable built-in and local declarative component adapters.

Connect to the local Multisim Automation API.

Create an editable Multisim schematic from a supported SPICE netlist. Supports RLC components, scalar/waveform voltage and current sources, B/E/F/G/H/T primitives, modeled semiconductors and switches, OPAMP5, and user-local verified TIMER8/LM555CN and DFF8/7474N native carriers, generic two-to-sixteen-terminal X subcircuits, digital devices, ground, named nets, wiring, and deterministic layout. Compatible inline subcircuits are recursively expanded into editable primitives; unsupported macro-model constructs remain explicit carrier-only evidence. Generated schematic probes remain experimental. The high-level experiment tool obtains authoritative data from the same source netlist through Multisim's command engine. When ``executable_netlist`` and ``netlist_approval`` are both supplied, the approval is revalidated against the immutable compiled preview before any schematic work begins. The supplied ``netlist`` must exactly match the approved preview's bound SPICE text. This path opens schematic generation only; it does not approve or start a simulation.

Decode a .ms14 file to editable XML using ewd.

Diagnose a circuit without modifying it or silently guessing repairs. Structural checks require only ``design``. When ``experiment_dir`` is supplied, its artifact integrity manifest and canonical netlist are verified before requirement, convergence, BJT, or op-amp evidence is used. An optional bounded ``simulation_failure`` object may contain code, type, stage, and message fields from a failed run.

Disconnect from Multisim and release the open circuit.

Run an unrestricted Multisim command file when explicitly enabled. This advanced tool is disabled by default because command files can access the filesystem and may expose engine-specific command execution features.

Encode an XML design back to .ms14 using ewe.

List component reference designators. 0 returns all.

List simulation inputs. 0 returns all.

List simulation outputs. 0 returns all.

Retest one explicit reversible patch against its unchanged baseline. The service runs exactly two verified experiments under the same hard requirements, writes before/after deterministic diagnoses and an inverse patch, and never persists the candidate as the source design. A passing result remains subject to the separate local approval workflow.

Export an artifact beneath MULTISIM_MCP_ARTIFACT_EXPORT_DIR.

Export bilingual HTML/PDF reports and a reproducibility manifest.

Write a Markdown report for the open circuit and analysis results.

Export the circuit schematic as an image.

Return durable progress, failure diagnostics, or the completed result.

Return a compact report, verification, and artifact summary for agents.

Fetch data for an output that is ready; shape depends on analysis type.

Read the current value of an R/L/C component through RLCValue.

Run auditable mixed topology/value multi-objective global optimization. Small declared domains are exhaustive; larger domains use deterministic Halton space filling. Every candidate runs a real verified experiment, failed hard constraints are excluded, and the result contains an epsilon-aware Pareto front. No candidate is persisted automatically.

List artifact metadata, hashes, MIME types, and safe access capabilities.

List recent durable jobs without returning their potentially large results.

Compute explicit metrics from a registered experiment's raw data.

Create a new empty Multisim design.

Open a Multisim design file and return circuit info.

Evaluate bounded component-value candidates without modifying the source design. The baseline consumes one experiment from ``spec.max_experiments``. Values may be explicit or generated from bounded E12/E24/E48/E96 ranges. Electrical, optional in-stock, and maximum variable-cost rules are hard constraints; failed/unverified candidates are never feasible, and the returned best patch still requires the separate local approval workflow before persistence.

Return comparable technical方案 without generating or executing a circuit. The result is a bounded planning-only ``DesignPlan``. It contains a deterministic recommendation, alternative implementation paths, trade-offs, and explicit assumptions. Netlists, schematics, files, and simulations are intentionally deferred until a caller selects an option in a later step.

Validate and preview parameter, tolerance, temperature, or Monte Carlo runs.

Prepare a reviewable electrical specification from a selected plan. This read-only step lists required electrical parameters, planned modules, analyses, and validation gates. It requires a valid selection digest and never creates a CircuitDesign, netlist, schematic, file, or simulation.

Prepare a logical netlist draft after explicit specification approval. The result contains block-level nets, connections, unresolved component requirements, and derived constraints. It is not executable SPICE and never creates a CircuitDesign, schematic, file, or simulation.

Read one bounded page from an allowlisted text experiment artifact.

Read DC, true RMS, AC RMS and range from experiment data.

Register an existing complete experiment directory as MCP Resources. Use this after a server restart when the experiment was generated earlier. Only the fixed high-level experiment artifact set is exposed.

Register a completed sweep directory and return opaque MCP Resources.