EmbeddedCI BenchPod

One calibrated voltage: ext = front SMA (true volts), cal1/cal2 = DAC loopbacks, amp = current terminal. Refused while the input is still moving (e.g. a DAC output left running).

Set every analog mux and relay for a named path in one step. dac_3v3/dac_5v/dac_12v route the DAC to an output; adc_ext connects the ADC to the front SMA; cal1/cal2 loop the 5 V/12 V DAC output back into the ADC; amp reads the current terminal; off parks everything.

Clear responder rules and stop CAN (safe when not open).

Bring up the pod's CAN interface (replacing any open CAN session).

Read received CAN frames (id, data, timestamps in pod milliseconds).

Make the pod firmware answer a CAN id instantly (ECU simulation), or clear all rules.

CAN link state: mode, bitrate, error counters, bus-off.

Queue one classic CAN frame.

Capture the ADC and summarise it: calibrated stats, dominant frequency and a min/max envelope. Above 32768 samples the capture streams from PSRAM (multi-second captures work). With trigger_la the capture waits for that edge or level, so t = 0 is the trigger moment. The capture is kept for replay and save_capture_as_recording.

ADC and LA captured from one hardware trigger, so their timebases align. Both are kept. With trigger_la both streams start on that edge or level.

Capture all 14 LA channels and summarise each: levels, edge count, first edge, estimated frequency. With trigger_la the capture starts on that edge or level instead of immediately, so a short event can be caught at a high sample rate. The capture is kept for decode_la and la_timing.

Record the DUT's UART output for a fixed window (or until until_regex matches). The channels and baud come from the wiring profile when omitted.

Escape hatch for firmware commands no tool covers. Prefer the dedicated tools.

Open a BenchPod connection (closing any previous one and its sessions) and report status. Over the cloud the device is shared: this takes an exclusive lease, released by `disconnect` or after the server's idle timeout (the next tool call then reconnects).

Run a tabulated transfer function in the FPGA: each tick out = curve[input], damped and clamped. Needs the loop gateware image, switched to automatically. Poll with loop_probe, move the input with loop_input, stop with dac_stop.

Route a DAC output (3v3, 5v, 12v = ±12 V, or off) and drive a calibrated DC voltage on it.

Stop any DAC output: generator, replay or control loop.

Decode I2C (sda, scl), UART (rx, baud) or SPI (sclk + mosi/miso/cs, mode) from LA data. Sample at least ~10x the bit rate. Decoding the last capture again with other channels is free.

Disarm the emulated sensor (safe when none is active).

Close UART/CAN sessions and the connection, releasing a cloud lease. Safe when not connected.

Make the pod act as a BMP280 on sda/scl for the DUT to read. Engage pull-ups on both lines first (set_pull). The channels and address come from the wiring profile when omitted.

Program the DUT over SWD through the pod's CMSIS-DAP probe (OpenOCD runs on this server's host). The SWD pins, the reset flag and the target config come from the wiring profile when omitted. A failed flash is a normal result (ok=false): read target_unreachable (unpowered, mis-wired or held in reset), stalled, and the log tails to decide what to change.

Reprogram the pod's FPGA with another stored gateware image (~2-3 s). Rarely needed: control_loop, replay and replay_waveform switch automatically. The switch resets the FPGA (any DAC output, UART session or I2C sensor emulation stops).

Drive a sine, square or sawtooth on a DAC output (built from 8-bit levels).

Claim LA channels as GPIO so the pod can drive or read them. A channel stays GPIO — across disconnects — until gpio_release, and while it is GPIO nothing else can use it: release it before uart_open, flash or enable_i2c_sensor on that channel. A channel already owned by another function is refused with a PinConflictError naming the owner, and an engaged bias resistor that would fight the mode with a PullConflictError.

Emit FPGA-timed pulses on an LA channel — a trigger for the DUT, or a step/dir motor train. The channel must be free or a GPIO output at level 0 (it returns to its GPIO level afterwards). The FPGA runs the train by itself, so this returns as soon as it starts.

The live level (0/1) of LA channels — omit `la` for all 14. Works whatever owns a channel; a GPIO input is the usual way to watch a DUT output.

Stop using channels as GPIO — they go back to high-Z, watched by captures. Omit `la` to release every GPIO channel (channels owned by other functions are left alone). Do this before starting a UART session, flashing or emulating a sensor on those channels.

Wait until an LA channel reads `level` (reached=false when the timeout passes first). Polled from this host, so it resolves to a few milliseconds plus the round trip — for precise timing use a triggered capture (capture_la trigger_la) and la_timing instead.

Set the level of GPIO output / open-drain channels (all of them in one pod command). The channels must already be in an output or open_drain mode (gpio_mode).

Capture and decode the emulated sensor's I2C bus into a transaction trace (S/Sr/P, addr, data, ACK).

Read the emulated sensor's register image.

Emulated sensor state plus bus activity counters — did the DUT talk to it at all?

What owns each of the 14 LA channels — none (free), gpio, uart_rx/uart_tx, swd_clk/swd_dio, i2c_sda/i2c_scl or step — plus each channel's GPIO mode, commanded level and bias resistor. Read this when a tool is refused with a pin conflict: it names the owner to stop. Live pin levels come along when the gateware can read them. Captures observe every channel whatever owns it.

Emit step pulses on an LA channel (step/dir motor drivers); with dir_la, set direction first. The FPGA runs the train by itself; this returns as soon as it starts.

Timing of one channel of the last capture_la / capture_correlated: edge timestamps, pulse widths, frequency and duty cycle; with to_la, the delay from its first edge to the next edge on to_la (e.g. a trigger pin to a "result ready" pin). Resolution is one sample; no new capture is taken.

The organisation's cloud waveform library (needs a cloud connection or BENCHPOD_API_KEY).

Re-target the running loop's input without re-arming (hold a point, meter, move on).

The running loop's live operating point; assert against loop_input, not i, in open-loop runs.

Measure the DUT's supply current and voltage for a window: average, minimum and peak current, voltage, energy and charge (gap-free sampling, so energy is integrated, not estimated). Use this for a self-contained window (a boot, a sleep interval). To profile across other tool calls, bracket them with power_profile_start / power_profile_stop.

Power the target off, then capture UART while it powers back on — the boot banner lands in the window. The channels, baud and power rail come from the wiring profile when omitted.

Switch the target's power rail off. The result says which rail was used.

Switch the target's power rail on. The result says which rail was used.

Start sampling the target-power rail in the background, then run the steps you want to profile and call power_profile_stop. Replaces any profile already running.

Stop the running power profile and return its statistics (and, with points, a trace).

Both target-power rails: eFuse on/off and tripped state, bus voltage and current draw.

State, direction and value of the bias resistor on LA1-LA8.