Koppar

Search KiCad's standard symbol libraries for parts whose name contains a substring. Use this whenever you are not 100% sure the (library, name) pair you're about to pass to Part(...) exists. Always prefer the package-suffixed variant the search returns over a generic name. If a part returns nothing here, get_kicad_symbol(library='custom', name='<part number>') may find it in the component database (a datasheet link and a pinout lead); register it with create_custom_symbol. Pass design_id so the lookup is recorded for the design's dossier and a registered part belongs to it.

Upload the released board (Gerbers, BOM, placement) to a manufacturer and return the page where the user pays. This publishes the design to a third party: call it only when the user has explicitly asked to order from that provider, and set user_confirmed only then. Some providers need a shipping address.

Replace everything on Edge.Cuts with a new outline: rect (optionally with corner_radius_mm), a polygon of points, or fit_to_parts (the rectangle around every footprint courtyard plus margin_mm). Give exactly one.

Set the project design rules (.kicad_pro) and copper layer count. Works on a board workspace and on a generated design (create_design → start_board). On a generated design the rules go into circuit.kicad_pro/.kicad_dru in place (the previous ones are snapshotted under rules_revisions/), are kept by every later project write (project.zip, a new board run), the copper is not changed and KiCad DRC judges the board against them at once: the reply carries the DRC counts and whether the Gerbers are released; the next start_board routes to the default_* values. copper_layers, stackup and board_thickness_mm are workspace-only (a generated design changes them with a new board). preset "jlcpcb" applies JLCPCB's published minimums for the layer count and writes their per-feature limits (plated rings, pad hole spacing, hole-to-track) as KiCad custom rules (.kicad_dru) that run_drc checks; explicit values override the minimums. Board minimums (min_*), the Default net class (default_*), and named net classes with their net patterns. route_board routes with these rules and run_drc checks against them. Changing copper_layers rebuilds the stackup; tracks on removed layers are reported. copper_layers 1 is a single-sided board (hand etching): the KiCad file keeps F.Cu and B.Cu, and from then on the routers hold to one face (B.Cu as soon as a THT pad exists, else F.Cu) and place no via; copper on the other face is removed.

Add or remove keepout rule areas. Each keepout is a rect or polygon on the given copper layers (default all) and forbids what it names: no_tracks, no_vias, no_zone_fills (all three default true), no_pads, no_footprints. route_board keeps tracks and vias out of them and KiCad DRC enforces them. remove takes names (wildcards allowed).

Take clutter off the silkscreen. values "hide" (default) hides value and part-number fields; references "keep" (default), "fab" (moved to the fabrication layer) or "hide"; texts "fab" moves footprint texts off the silkscreen. run_drc's silk_overlap and silk_over_copper warnings count what is left.

Add or remove copper zones (pours). Each zone pours its net on the given copper layers over rect or polygon, by default the whole board outline. priority orders overlapping zones (higher fills first); clearance_mm and min_thickness_mm override the rules; thermal false connects pads solid. remove takes zone or net names (wildcards allowed) and never touches keepout areas. Run fill_zones afterwards, then run_drc.

Silkscreen stamps for release, both off unless asked for: a small spec badge ("routed with Koppar", optionally the title, revision and part count) in the largest free patch of the front or back silk, and JLCPCB's JLCJLCJLCJLC placeholder on the back silk so their order number is printed there, not on the front. Free means clear of pads, mask openings, other silk, courtyards, holes and the edge. KiCad's DRC is run before and after and a stamp that changes any count is taken off again.

Start place and route with your board plan (the JSON object from the board guide: board, stated, edge, chain, groups, near, side, fixed, keepouts, netClasses). The plan is clamped and returned as applied. Runs for minutes in the background: follow it with get_board_status. Needs an accepted schematic; one board run per design at a time.

Compile and check a complete SKiDL script: the symbol and footprint pre-flight (unambiguous typos are corrected and listed), SKiDL, the ERC score, KiCad ERC, floating subsystems, parts without a footprint, and supplier sourcing. Returns accepted plus blocking findings to fix and warnings. An accepted script becomes the design's circuit.py; one that is sent back is kept as attempt_N_circuit.py and leaves the design as it was. Takes up to a couple of minutes.

Replace footprints in place with another footprint from a library in the project's fp-lib-table (library:name): the reference, value, position, rotation (or rot_deg), side, lock and schematic link stay, and nets move pad by pad. pad_map maps a NEW pad number to the OLD pad whose net it takes, for packages numbered differently. The schematic symbols' Footprint fields are updated too. Reports new pads left without a net and old nets left behind.

After routing: every run redrawn as the fewest 0/45/90-degree segments that clear, and every track narrower than its net's netclass width widened where it fits (slid sideways, bumped around a lone obstacle, or necked only over the stretch that needs it; a via or thin track of another net moved aside when that is all that is in the way). No via is added or removed; a change that would split a pour is undone, and the board is kept only if KiCad counts nothing worse.

Tie neighbouring same-net SMD pads of the plane nets (GND, the rails with a pour) together on their own layer with short tracks, so a group shares one via to the plane instead of one via per pad, as a designer does. A tie is placed only where it misses every other net's pad, its tracks and vias, and the board edge. Before routing: route afterwards with preserve_existing (the default). After routing and prune_vias: run prune_vias on those nets again.

Replace the design's board with a .kicad_pcb you routed or edited yourself (the file, base64). The board must carry the design's circuit: every schematic part by reference, every pad on the net the netlist gives it; a footprint swap is allowed and recorded. Anything else is refused with the list of differences and nothing changes. The previous board is kept as circuit.before-upload.kicad_pcb. KiCad DRC judges the new board and releases or withholds the Gerbers, and the session chat gets a note of the upload. Not for a board workspace (import_kicad_project): its board tools edit the board in place.

Grow the tracks (and optionally vias) of the named nets in place, each as wide as its clearance to every other net's copper, holes and the board edge allows, up to the net's target width. Nothing moves and no via is added, so the score does not change. Routers neck power down to the signal width wherever the class width did not fit their grid; most necks have room around them. List the heaviest current first: earlier nets take the room. Pours are refilled after each net and a widening that leaves the board less connected is backed out. The result names what still holds each remaining neck (a neighbour to move or reroute).